We explain what non-volatile memory is and why RRAM and MRAM (Resistive and Magneto-Resistive Random Access Memory) are taking over for embedded flash memory. The post Flash Forward: MRAM and R...
https://www.synopsys.com/blogs/chip-design/rram-mram-non-volatile-memory.html
We explain what Hardware-Assisted Verification (HAV) is and explore its impact on hardware architecture, software-defined solutions, and the chip design flow. The post Hardware-Assisted Verific...
https://www.synopsys.com/blogs/chip-design/what-is-hardware-assisted-verification-hav.html
From RF design migration to interface IP and multi-die chip design tools, we received multiple TSMC Partner of the Year awards at the 2024 OIP Ecosystem Forum. The post From TSMC A16 and Multi-...
https://www.synopsys.com/blogs/chip-design/tsmc-partner-of-the-year-2024.html
Learn how to accelerate AI chip design simulation with cloud-based chip emulation tools for secure, pre-silicon chip validation in a flexible cloud environment. The post Accelerating AI Chip De...
https://www.synopsys.com/blogs/chip-design/cloud-ai-chip-emulation.html
We explain how Static Random-Access Memory Physical Unclonable Function (SRAM PUF) enhances chip security with silicon fingerprints and cryptographic keys. The post Why SRAM PUF Technology Is t...
https://www.synopsys.com/blogs/chip-design/sram-puf-chip-security.html
Learn about our company-wide Pitch Fest, a contest that fosters semiconductor innovation across chip verification, global energy consumption, and beyond. The post Fostering a Culture of Innovat...
https://www.synopsys.com/blogs/chip-design/pitch-fest-semiconductor-innovation.html
We unpack why AI chip startups turn to EDA tools in the cloud, from easily scalable chip design verification to baked-in semiconductor foundry compliance. The post AI Chip Startups Turn to the ...
https://www.synopsys.com/blogs/chip-design/ai-chip-startups-cloud-eda-tools.html
Our new 40G Universal Chip Interconnect Express (UCIe) IP, delivers 25% more bandwidth for die to die connectivity in multi-die Data Center AI Chips. The post Synopsys Introduces Industry’s F...
See how NVIDIA used our functional chip verification tool VSO.ai to achieve 33% faster coverage closure by identifying more chip design bugs early on. The post Reducing Manual Effort and Achiev...
https://www.synopsys.com/blogs/chip-design/vso-ai-nvidia.html
We're leveraging edge analytics for software defined vehicles, helping automotive OEMs improve silicon lifecycle management via our work w/ BlackBerry & AWS. The post Combining Silicon Data Cap...
https://www.synopsys.com/blogs/chip-design/software-defined-vehicles-blackberry-aws.html
Learn about the benefits of CMOS-driven cryogenic computing for AI power consumption and explore our work with Semiwise on low-temperature semiconductor design. The post Can Sub-Arctic Temperat...
https://www.synopsys.com/blogs/chip-design/cryogenic-cmos-computing-semiwise.html
Unpack the latest in AI chip design from Hot Chips 2024, from new semiconductor IP to hardware-assisted verification tools for chiplets and wafer-scale designs. The post Accelerating the Pace a...
https://www.synopsys.com/blogs/chip-design/ai-chip-design-hot-chips-2024.html
Our 2023 environmental, social, and governance (ESG) report explores how we're powering the innovations that shape a smart future of pervasive intelligence. The post Synopsys Releases 2023 ESG ...
https://www.synopsys.com/blogs/chip-design/2023-esg-report.html
We explore fixes for Silent Data Corruption (SDC) issues, including how semiconductor industry collaboration and better data reduce errors in data processing. The post Ecosystem Collaboration &...
https://www.synopsys.com/blogs/chip-design/silent-data-corruption-sdc-challenges.html
We celebrate the second anniversary of the U.S. CHIPS and Science Act with a look forward at the next step: $13 billion in research and development funds. The post In Its Second Year, U.S. CHIP...
https://www.synopsys.com/blogs/chip-design/chips-act-research-development.html